The MSS I/Os must only appear under the MSS pdc file.įolks at Actel seem to have forgotten what simple and intuitive means. But not only must you add this file, you must also remove any reference to the incorrectly placed constraints from the original pdc file. I imagine that if you hit the Designer button in Libero it will add the new pdc file to the Designer project, but as I rarely hit that button, b/c Designer is already open, I can't say whether this is true. That's not all folks! Now you must add a new pdc file to the Designer project. The solution? Under the MSS configurator there is a middle tab for I/O Attributes. Why is that bad? Because they don't work! The moment you attempt to compile in Designer, you get a strange error message telling you how you can't modify these IO settings! What is even more strange is that if you edit that pdc file in the I/O Attribute Editor, you see the MSS I/Os and they offer to enable Schmitt Triggers. pdc is no longer the file for these constraints. What is overly confusing is how the default constraints file located under component/work/ /. I did this because I needed Schmitt Triggers. I recently configured an MSS I/O to route to the FPGA. Even if they tried to automate something, they still let you override whatever it is.Īnother frustrating problem is how Libero splits constraints into 2 places. Their tools are not great, but they leave all of the configuration in your hands. Xilinx is an example of a high quality company that doesn't over-engineer (from what I recall). It also opens the door to many more bugs. Over engineering creates for confusion as nothing is intuitive anymore. I am referring to customers as the users and the Actel employed programmers as the developers.
Therefore, the user should be aware of these varying interpretations if latches are specied with no controlling clocks. In general, over-engineering complicates both users' and developers' lives. The behavior of this global clock may be interpreted differently by the various algorithms that may manipulate the model after the model has been read in. Divide GLA by 3 and the constraint is set as if it was divided by 2. Libero has a bug where it sets the constraint incorrectly if you set the divider of GLx to a non power of 2. These constraints can't be edited using Designer's constraint editor because the automatic constraints are read-only. There is no pdc file to edit for the clock constraints. Those constraints are then hard wired into the Designer project. Libero determines all of your clock constraints from the MSS setup. the disadvantage is Actel and their tools.Īctel has violated a rule in design. I have been using the SmartFusion FPGA for a while now.
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